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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max1715 pwm controller provides the high effi- ciency, excellent transient response, and high dc out- put accuracy needed for stepping down high-voltage batteries to generate low-voltage cpu core, i/o, and chipset ram supplies in notebook computers. maxim? proprietary quick-pwm quick-response, constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant-on?response to load transients while maintaining a relatively constant switching frequency. the max1715 achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode pwms. efficiency is further enhanced by its ability to drive very large synchronous- rectifier mosfets. single-stage buck conversion allows this device to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two-stage conversion (stepping down the +5v system supply instead of the battery) at a higher switching frequency allows the mini- mum possible physical size. the max1715 is intended for cpu core, chipset, dram, or other low-voltage supplies as low as 1v. the max1715 is available in a 28-pin qsop package. for applications requiring vid compliance or dac control of output voltage, refer to the max1710/max1711 data sheet. for a single-output version, refer to the max1714 data sheet. applications notebook computers cpu core supply chipset/ram supply as low as 1v 1.8v and 2.5v i/o supply features ultra-high efficiency no current-sense resistor (lossless i limit ) quick-pwm with 100ns load-step response 1% v out accuracy over line and load dual-mode fixed 1.8v/3.3v/adj or 2.5v/adj outputs adjustable 1v to 5.5v output range 2v to 28v battery input range 200/300/420/540khz nominal switching frequency over/undervoltage protection 1.7ms digital soft-start drives large synchronous-rectifier fets power-good indicator max1715 ultra-high efficiency, dual step-down controller for notebook computers ________________________________________________________________ maxim integrated products 1 19-1541; rev 0; 1/00 pin configuration appears at end of data sheet. quick-pwm is a trademark of maxim integrated products. -40? to +85? part MAX1715EEI temp. range pin-package 28 qsop ordering information evaluation kit available v cc output1 1.8v battery 4.5v to 28v ilim1 on2 dl1 ton out1 lx1 dh1 fb1 agnd v dd bst1 ilim2 on1 ref dl2 pgnd out2 lx2 dh2 fb2 v+ bst2 skip 5v input pgood output2 2.5v max1715 minimal operating circuit
max1715 ultra-high efficiency, dual step-down controller for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to agnd..............................................................-0.3 to +30v v dd , v cc to agnd..................................................-0.3v to +6v pgnd to agnd or v cc to v dd ...........................................?.3v pgood, out_ to agnd..........................................-0.3v to +6v ilim_, fb_, ref, skip , ton, on_ to agnd ...........................................-0.3v to (v dd + 0.3v) dl_ to pgnd ..............................................-0.3v to (v dd + 0.3v) bst_ to agnd........................................................-0.3v to +36v dh1 to lx1 ...............................................-0.3v to (bst1 + 0.3v) dh2 to lx2 ...............................................-0.3v to (bst2 + 0.3v) lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v ref short circuit to agnd.........................................continuous continuous power dissipation (t a = +70?) 28-pin qsop (derate 8.0mw/? above +70?).....640mw/? operating temperature range ..........................-40? to +85? junction temperature ......................................................+150? storage temperature range ............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (circuit of figure 1, 4a components from table 1, v cc = v dd = +5v, skip = agnd, v+ = 15v, t a = 0? to +85? , unless otherwise noted.) (note 1) i load = 0 to 4a, each output % 0.4 fb2 = gnd battery voltage, v+ input voltage range v+ = 24v, out2 = 2v load regulation error v cc = 4.5v to 5.5v, v+ = 4.5v to 28v v+ = 24v, out1 = 2v adjustable mode, each output output 2 error comparator threshold (dc output voltage accuracy) (note 2) ton = gnd fb_ input bias current ton = gnd ton = open v out _ = agnd 210 247 280 conditions v ton = ref 142 173 205 ms ton = v dd out_ input resistance ? soft-start ramp time ? fb_ = agnd rising edge of on_ to full current limit 2.475 2.5 2.525 v+ = 2v to 28v, skip = v cc , t a = +25? i load = 0 to 4a v+ = 2v to 28v, skip = v cc , t a = +25? i load = 0 to 4a ns 154 182 215 v on-time (pwm2) ns 112 136 160 0.99 1.00 1.01 on-time (pwm1) v 1.7 0.99 1.00 1.01 300 353 407 1.782 1.8 1.818 -0.1 0.1 ton = open 292 336 380 ton = ref 75k 3.267 3.3 3.333 fb1 = v cc fb1 = agnd fb1 = out1 228 fb2 = out2 v 1 5.5 output voltage range % 0.2 198 234 270 line regulation error ton = v dd 420 484 550 units min typ max parameter output 1 error comparator threshold (dc output voltage accuracy) (note 2) 4.5 5.5 v dd, v cc output 1 error comparator threshold (dc output voltage accuracy) (note 2) v+ = 2v to 28v, skip = v cc , t a = 0? to +85? i load = 0 to 4a v 0.985 1.00 1.105 1.773 1.8 1.827 3.250 3.3 3.350 fb1 = v cc fb1 = agnd fb1 = out1 fb2 = gnd output 2 error comparator threshold (dc output voltage accuracy) (note 2) 2.463 2.5 2.538 v+ = 2v to 28v, skip = v cc , t a = 0? to +85? i load = 0 to 4a v 0.985 1.00 1.105 fb2 = out2
max1715 ultra-high efficiency, dual step-down controller for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, 4a components from table 1, v cc = v dd = +5v, skip = agnd, v+ = 15v, t a = 0? to +85? , unless otherwise noted.) (note 1) (note 3) ns 400 500 minimum off-time i ref = 0 to 50? no external ref load on1 = on2 = 0 v 2 0.01 reference load regulation v 1.98 2 2.02 reference voltage ? <1 5 shutdown supply current (v+) ? <1 5 shutdown supply current (v cc + v dd ) falling edge, hysteresis = 40mv v 1.6 ref fault lockout voltage 10 pgnd - lx_, i lim resistor = 100k ? mv 40 50 60 current-limit threshold (positive direction, adjusted) pgnd - lx_, t a = +25?, i lim = v cc mv -145 -120 -95 current-limit threshold (negative direction) pgnd - lx_, skip = agnd mv -5 3 10 current-limit threshold, zero crossing hysteresis = 10? ? 150 thermal shutdown threshold rising edge, hysteresis = 20mv, pwm disabled below this level v 4.1 4.4 v cc undervoltage lockout threshold bst - lx forced to 5v ? 1.5 5 dh gate driver on-resistance fb1 and fb2 forced above the regulation point ? 1100 1600 quiescent supply current (v cc + v dd ) ? 25 70 quiescent battery current (v+) fb_ forced 2% above trip threshold ? 1.5 overvoltage fault propagation delay with respect to error comparator threshold % 8.5 10.5 13 overvoltage trip threshold with respect to error comparator threshold % 60 70 80 output undervoltage threshold from on_ signal going high ms 10 20 30 output undervoltage lockout time pgnd - lx_, i lim = v cc mv 75 100 125 current-limit threshold (positive direction, fixed) on1 = on2 = 0 dl, high state ? 1.5 5 dl gate driver on-resistance (pull-up) 0.6 2.5 a dh gate driver source/sink current dh forced to 2.5v, bst_ - lx_ forced to 5v 1 a dl gate driver source current dl forced to 2.5v 1 a dl gate driver sink current dl forced to 2.5v 3 ns dead time dl rising 35 ref in regulation ref sink current dl, low state dl gate driver on-resistance (pull-down) ? ? conditions units min typ max parameter pgnd - lx_, i lim resistor = 400k ? 160 200 240 dh rising 26 on_, skip 0.8 v logic input high voltage on_, skip 2.4 v logic input low voltage
max1715 ultra-high efficiency, dual step-down controller for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1, 4a components from table 1, v cc = v dd = +5v, skip = agnd, v+ = 15v, t a = -40? to +85? , unless otherwise noted.) (note 1) electrical characteristics (continued) (circuit of figure 1, 4a components from table 1, v cc = v dd = +5v, skip = agnd, v+ = 15v, t a = 0? to +85? , unless otherwise noted.) (note 1) conditions v cc level v v cc - 0.4 ton threshold float level 3.15 3.85 ref level 1.65 2.35 agnd level 0.5 ton (0 or v cc ) ? -3 3 logic input current units min typ max parameter on-time (pwm1) 112 136 160 ns fb2 = gnd fb2 = out2 v+ = 4.5v to 28v, skip = v cc 3.234 3.3 3.372 fb1 = v cc fb1 = agnd fb1 = out1 1.764 1.8 1.836 minimum off-time 400 500 ns (note 3) 2.45 2.5 2.55 output 2 error comparator threshold (dc output voltage accuracy) (note 2) 0.98 1.00 1.02 v parameter min typ max units input voltage range 228 v 4.5 5.5 output 1 error comparator threshold (dc output voltage accuracy) (note 2) 0.98 1.00 1.02 v conditions battery voltage, v+ v dd, v cc v+ = 2v to 28v, skip = v cc on-time (pwm2) 154 182 215 ns on_, skip (0 or v cc ) ? -1 1 logic input current falling edge, fb_ forced 2% below pgood trip threshold ? 1.5 pgood propagation delay measured at fb_, with respect to error comparator threshold, no load % -8 -5.5 -4 pgood trip threshold i sink = 1ma v 0.1 0.4 pgood output low voltage high state, forced to 5.5v ? 1 pgood leakage current skip , to deactivate ovp circuitry ma -5 -1 logic input current 210 247 280 142 173 205 300 353 407 292 336 380 198 234 270 v+ = 24v, out2 = 2v 420 484 550 ton = gnd ton = ref ton = open ton = v dd v+ = 24v, out1 = 2v ton = gnd ton = ref ton = open ton = v dd
max1715 ultra-high efficiency, dual step-down controller for notebook computers _______________________________________________________________________________________ 5 60 0.01 10 1 0.1 90 100 80 70 max1715-01 load current (a) efficiency (%) efficiency vs. load current (1.8v, 4a components, skip = gnd) v+ = +7v v+ = +12v v+ = +20v 0 0.01 10 1 0.1 60 80 100 40 20 max1715-02 load current (a) efficiency (%) efficiency vs. load current (1.8v, 4a components, skip = v cc ) v+ = +7v v+ = +20v v+ = +12v 60 0.01 10 1 0.1 90 100 80 70 max1715-03 load current (a) efficiency (%) efficiency vs. load current (2.5v, 4a components, skip = gnd) v+ = +7v v+ = +20v v+ = +12v note 1: specifications to -40? are guaranteed by design, and not production tested. note 2: when the inductor is in continuous conduction, the output voltage will have a dc regulation higher than the trip level by 50% of the ripple. in discontinuous conduction ( skip = agnd, light load) the output voltage will have dc regulation higher than the trip level by approximately 1.5% due to slope compensation. note 3: on-time and off-time specifications are measured from the 50% point at the dh pin with lx = pgnd, v bst = 5v. actual in-circuit times may differ due to mosfet switching speeds. __________________________________________typical operating characteristics (circuit of figure 1, components from table 1, v in = +15v, skip = agnd, ton = unconnected, t a = +25?, unless otherwise noted.) electrical characteristics (continued) (circuit of figure 1, 4a components from table 1, v cc = v dd = +5v, skip = agnd, v+ = 15v, t a = -40? to +85? , unless otherwise noted.) (note 1) quiescent battery current (v+) 25 70 ? reference voltage 1.97 2 2.03 v no external ref load quiescent supply current (v cc + v dd ) 1100 1600 ? fb1 and fb2 forced above the regulation point parameter min typ max units conditions reference load regulation 0.01 v i ref = 0 to 50? overvoltage trip threshold 10 12.5 15 % with respect to error comparator threshold output undervoltage threshold 60 70 80 % with respect to error comparator threshold current-limit threshold (positive direction, fixed) 75 100 125 mv pgnd - lx_, i lim = v cc current-limit threshold (positive direction, adjusted) 32 50 62 mv pgnd - lx_, i lim resistor = 100k ? pgnd - lx_, i lim resistor = 400k ? 160 200 240 thermal shutdown threshold 150 ? hysteresis = 10? rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v v cc undervoltage lockout threshold logic input high voltage 2.4 v on_, skip on_, skip 0.8 v logic input low voltage skip , to deactivate ovp circuitry -5 -1 ma logic input current
max1715 ultra-high efficiency, dual step-down controller for notebook computers 6 _______________________________________________________________________________________ _____________________________typical operating characteristics (continued) (circuit of figure 1, components from table 1, v in = +15v, skip = agnd, ton = unconnected, t a = +25?, unless otherwise noted.) 0 0.01 10 1 0.1 60 80 100 40 20 max1715-9 load current (a) efficiency (%) efficiency vs. load current (1.3v, 8a components, skip = v cc ) v+ = +7v v+ = +20v v+ = +12v 0 0.01 10 1 0.1 300 400 200 100 max1715-10 load current (a) frequency (khz) frequency vs. load current (4a components) out1, skip = v cc out2, skip = v cc out1, skip = gnd out2, skip = gnd 400 300 200 100 0 412 8 162024 max1715-11 supply voltage (v) frequency (khz) frequency vs. supply voltage (4a components, skip = v cc ) out1 out2 100 80 60 40 20 0 0.001 0.1 1 0.01 10 max1715-07 load current (a) efficiency (%) efficiency vs. load current (3.3v, 1.5a components, v in = 5v) skip = v cc skip = gnd 60 0.01 10 1 0.1 80 100 max1715-08 load current (a) efficiency (%) efficiency vs. load current (1.3v, 8a components, skip = gnd) v+ = +7v v+ = +20v v+ = +12v 0 0.01 10 1 0.1 60 80 100 40 20 max1715-04 load current (a) efficiency (%) efficiency vs. load current (2.5v, 4a components, skip = v cc ) v+ = +7v v+ = +20v v+ = +12v 60 0.01 10 1 0.1 90 100 80 70 max1715-05 load current (a) efficiency (%) efficiency vs. load current (5v, 3a components, skip = gnd) v+ = +7v v+ = +20v v+ = +12v 0 0.01 10 1 0.1 60 80 100 40 20 max1715-06 load current (a) efficiency (%) efficiency vs. load current (5v, 3a components, skip = v cc ) v+ = +7v v+ = +20v v+ = +12v
300 200 250 150 100 50 0 -40 0 -20 40 20 60 80 max1715-12 temperature ( c) frequency (khz) frequency vs. temperature (2.5v, 4a components, skip = high) c a b max1715-16 a = v out , 2v/div b = inductor current, 2a/div c = dl, 10v/div start-up waveform (2.5v, 4a components, active load) 700 500 600 400 300 100 200 0 0 10 5 20 15 25 30 max1715-13 input voltage (v) supply current ( a) no-load supply current vs. input voltage (out1 = 1.8v, 4a components; out2 = 2.5v, 4a components; skip = gnd) i dd i cc i batt 12 8 10 6 4 2 0 0 10 5 20 15 25 30 max1715-14 input voltage (v) supply current (ma) no-load supply current vs. input voltage (out1 = 1.8v, 4a components; out2 = 2.5v, 4a components; skip = v cc ) i dd i cc i in c a b max1715-17 a = v out , ac-coupled, 100mv/div b = inductor current, 5a/div c = dl, 10v/div load-transient response (1.3v, 8a components, skip = gnd) max1715 ultra-high efficiency, dual step-down controller for notebook computers _______________________________________________________________________________________ 7 _____________________________typical operating characteristics (continued) (circuit of figure 1, components from table 1, v in = +15v, skip = agnd, ton = unconnected, t a = +25?, unless otherwise noted.) c a b max1715-19 a = v out , 2v/div b = inductor current, 5a/div c = dl, 10v/div shutdown waveform (2.5v, 4a components, skip = gnd) c a b max1715-18 a = v out , 2v/div b = inductor current, 5a/div c = dl, 10v/div output overload waveform (2.5v, 4a components, skip = gnd) c a b max1715-15 a = v out , ac-coupled, 100mv/div b = inductor current, 2a/div c = dl, 10v/div load-transient response (2.5v, 4a components, skip = gnd)
170 max1715 ultra-high efficiency, dual step-down controller for notebook computers 8 _______________________________________________________________________________________ pin description out1 on/ off control input. drive to agnd to turn out1 off. drive to v cc to turn out1 on. on1 10 feedback input for out1. connect to agnd for 1.8v fixed output or to v cc for 3.3v fixed output, or connect to a resistor-divider from out1 for an adjustable output. fb1 2 +2.0v reference voltage connection. bypass to agnd with 0.22? (min) capacitor. can supply 50? for external loads. ref 9 output voltage connection for the out1 pwm. connect directly to the junction of the external inductor and output filter capacitors. out1 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. out1 1 pulse-skipping control input. connect to v cc for low-noise forced-pwm mode. connect to agnd to enable pulse-skipping operation. skip 6 power-good open-drain output. pgood is low when either fb_ input is more than 5.5% below the normal regulation point (typ). pgood 7 analog ground agnd 8 current-limit threshold adjustment for out1. the lx1-pgnd current-limit threshold defaults to +100mv if ilim1 is connected to v cc . or, connect an external resistor to agnd to adjust the limit. a precision 5? pull-up current through r ext sets the threshold from 50mv to 200mv. the voltage on the pin is 10 times the current- limit voltage. choose r ext equal to 2k ? per mv of current-limit threshold (100k ? to 400k ? ). ilim1 3 battery voltage sense connection. connect to the input power source. v+ is used only to set the pwm one- shot timing. v+ 4 pin on-time selection control input. this is a four-level input used to determine dh_ on-time. the ton table below is for v in = 24v, v out1 = 1.8v, v out2 = 2.5v condition. ton 5 function name out2 on/ off control input. drive to agnd to turn out2 off. drive to v cc to turn out2 on. on2 11 current-limit threshold adjustment for out2. the lx2-pgnd current-limit threshold defaults to +100mv if ilim2 is connected to v cc . or, connect an external resistor to agnd to adjust the limit. a precision 5? pull-up current through r ext sets the threshold from 50mv to 200mv. the voltage on the pin is 10 times the current- limit voltage. choose r ext equal to 2k ? per mv of current-limit threshold (100k ? to 400k ? ). ilim2 12 feedback input for out2. connect to agnd for 2.5v fixed output, or connect to a resistor-divider from out2 for an adjustable output. fb2 13 output voltage connection for the out2 pwm. connect directly to the junction of the external inductor and output filter capacitors. out2 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output mode. out2 14 no connection. these pins are not connected to any internal circuitry. connect the n.c. pins to the ground plane to enhance thermal conductivity. n.c. 15, 23, 28 agnd ton open v cc ref 235 345 485 620 frequency (out1) (khz) frequency (out2) (khz) 460 355 255 170
max1715 ultra-high efficiency, dual step-down controller for notebook computers _______________________________________________________________________________________ 9 pin description (continued) high-side gate driver output for out1. swings from lx1 to bst1. dh1 26 high-side gate driver output for out2. swings from lx2 to bst2. dh2 17 boost flying capacitor connection for out1. connect to an external capacitor and diode according to the standard application circuit (figure 1). see mosfet gate drivers (dh_, dl_) section. bst1 25 external inductor connection for out2. connect to the switched side of the inductor. lx2 serves as the lower supply voltage rail for the dh2 high-side gate driver and is the positive input to the out2 current-limit comparator. lx2 16 analog-supply input. connect to the system supply voltage, +4.5v to +5.5v, with a 20 ? series resistor. bypass to agnd with a 1? ceramic capacitor. v cc 21 power ground. connect directly to the low-side mosfets?sources. serves as the negative input of the cur- rent-sense amplifiers. pgnd 22 low-side gate driver output for out1. dl1 swings pgnd to v dd . dl1 24 boost flying capacitor connection for out2. connect to an external capacitor and diode according to the standard application circuit (figure 1). see mosfet gate drivers (dh_, dl_) section. bst2 18 low-side gate-driver output for out2. dl2 swings from pgnd to v dd . dl2 19 pin supply input for the dl gate drivers. connect to the system supply voltage, +4.5v to +5.5v. bypass to pgnd with a minimum 4.7? ceramic capacitor. v dd 20 function name external inductor connection for out1. connect to the switched side of the inductor. lx1 serves as the lower supply voltage rail for the dh1 high-side gate driver. lx1 27
max1715 ultra-high efficiency, dual step-down controller for notebook computers 10 ______________________________________________________________________________________ v dd = 5v bias supply pins 15, 23, 28 = n.c. power-good indicator max1715 v cc output1 1.8v v in 4.5v to 28v d3 cmpsh-3a ilim1 on1 dl1 ton out1 agnd c3 c4 d1 n2 n4 n3 n1 lx1 dh1 c5 0.1f c6 0.1f c7 0.22f fb1 v dd c8 1f c1 20 21 25 26 27 24 5 1 9 2 8 10 11 18 17 16 19 22 14 6 13 7 c2 c11 1 f l1 12 3 l2 bst1 ilim2 ref on1 on2 dl2 pgnd +5v 100k out2 lx2 dh2 fb2 pgood v+ 4 bst2 skip c9 4.7f r1 20 ? output2 2.5v d2 on/off controls figure 1. standard application circuit standard application circuit the standard application circuit (figure 1) generates two low-voltage rails for general-purpose use in note- book computers (i/o supply, fixed cpu core supply, dram supply). this dc-dc converter steps down a battery or ac adapter voltage to voltages from 1.0v to 5.5v with high efficiency and accuracy. see table 1 for a list of components for common appli- cations. table 2 lists component manufacturers. detailed description the max1715 buck controller is designed for low-volt- age power supplies for notebook computers. maxim? proprietary quick-pwm pulse-width modulator in the max1715 (figure 2) is specifically designed for han- dling fast load steps while maintaining a relatively con- stant operating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode pwms while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time pwm schemes. +5v bias supply (v cc and v dd ) the max1715 requires an external +5v bias supply in addition to the battery. typically, this +5v bias supply is the notebook? 95% efficient +5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v supply can be generated with an external linear regulator such as the max1615.
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 11 the power input and +5v bias inputs can be connected together if the input source is a fixed +4.5v to +5.5v supply. if the +5v bias supply is powered up prior to the battery supply, the enable signal (on1, on2) must be delayed until the battery voltage is present to ensure start-up. the +5v bias supply must provide v cc and gate-drive power, so the maximum current drawn is: i bias = i cc + f (qg1 + qg2) = 5ma to 30ma (typ) where icc is 1ma typical, f is the switching frequency, and qg1 and qg2 are the mosfet data sheet total gate-charge specification limits at v gs = 5v. free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time current-mode type with voltage feed-forward (figure 3). this architecture relies on the output filter capacitor? esr to act as the cur- rent-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined sole- ly by a one-shot whose period is inversely proportional to input voltage and directly proportional to output volt- age. another one-shot sets a minimum off-time (400ns typ). the on-time one-shot is triggered if the error com- parator is low, the low-side switch current is below the table 1. component selection for standard applications table 2. component suppliers 4.75v to 5.5v 7v to 20v 7v to 20v input range 100?, 10v sanyo poscap 10tpa100m 470?, 4v sanyo poscap 4tpb470m 470?, 4v sanyo poscap 4tpb470m c2 output capacitor 100?, 10v sanyo poscap 10tpa100m 10?, 25v taiyo yuden tmk432bj106km 10?, 25v taiyo yuden tmk432bj106km c1 input capacitor 3.3? toko d73lc 3.1? sumida cdrh125 4.4? sumida cdrh125 l1 inductor nihon ep10qy03 nihon ep10qy03 d2 rectifier international rectifier 1/2 irf7301 fairchild semiconductor 1/2 fds6982a fairchild semiconductor 1/2 fds6982a q2 low-side mosfet international rectifier 1/2 irf7301 fairchild semiconductor 1/2 fds6982a fairchild semiconductor 1/2 fds6982a q1 high-side mosfet 600khz 345khz 255khz frequency 3.3v at 1.5a 1.8v at 4a 2.5v at 4a component [1] 602-994-6430 602-303-5454 motorola [1] 408-986-1442 408-986-0424 kemet [1] 408-721-1635 408-822-2181 fairchild semiconductor [1] 561-241-9339 561-241-7876 coiltronics [1] 847-639-1469 847-639-6400 coilcraft [1] 516-435-1824 516-435-1110 central semiconductor [1] 803-626-3123 803-946-0690 avx factory fax [country code] usa phone manufacturer [1] 714-960-6492 714-969-2491 matsuo [1] 310-322-3332 310-322-3331 international rectifier [1] 408-573-4159 408-573-4150 taiyo yuden [1] 603-224-1430 603-224-1961 sprague [1] 408-970-3950 408-988-8000 800-554-5565 siliconix [81] 7-2070-1174 619-661-6835 sanyo [81] 3-3494-7414 805-867-2555* niec (nihon) [1] 814-238-0490 814-237-1431 800-831-9172 murata [81] 3-3607-5144 847-956-0666 sumida [1] 847-390-4405 847-390-4461 tdk *distributor 7v to 20v (2) 470?, 6v kemet t510x477108m0 06as (2) 10?, 25v taiyo yuden tmk432bj106km 1.5? sumida cep125-1r5mc motorola mbrs340t3 fairchild semiconductor fds6670a international rectifier irf7811 255khz 1.3v at 8a 7v to 20v 330?, 6v avx tpsv337m006r 0060 10?, 25v taiyo yuden tmk432bj106km 6.8? coiltronics up2b nihon ep10qy03 fairchild semiconductor 1/2 fds6990a fairchild semiconductor 1/2 fds6990a 255khz 5v at 3a [1] 708-699-1194 800-pik-toko toko
max1715 ultra-high efficiency, dual step-down controller for notebook computers 12 ______________________________________________________________________________________ current-limit threshold, and the minimum off-time one- shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time for both controllers. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely pro- portional to the battery voltage as measured by the v+ input, and proportional to the output voltage. this algo- rithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the on-times for side 1 are set 15% higher than the 2v ref agnd ref out2 fb2 20 ? pgnd v dd output2 2.5v dl2 v cc v dd lx2 zero crossing current limit pwm controller (see figure 3) dh2 bst2 r i lim_ v dd v cc v+ v+ v+ out1 fb1 skip ton on1 on2 output1 1.8v 5v input dl1 v dd lx1 zero crossing current limit dh1 9r r i lim_ battery 4.5v to 28v 5 a bst1 v dd v dd v cc v dd v+ pwm controller (see figure 3) max1715 5 a 9r p good figure 2. functional diagram
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 13 ref -6% from out ref from zero-crossing comparator error amp toff ton ref +12% ref -30% feedback mux (see figure 9) x2 ovp/uvlo latch to dl driver to dh driver on-time compute ton 1-shot from ilim comparator 1-shot trig in 2v to 28v trig q q s r fb_ out_ q s1 q s2 timer ton v+ s r q to pgood or gate figure 3. pwm controller (one side only) x = don? care on1 on2 skip mode comments 0 0 x shutdown low-power shutdown state. dl = v dd . clears fault latches. 0 1 x out1 disable disable out1. dl1 = v dd . clears out1 fault latches. 1 0 x out2 disable disable out2. dl2 = v dd . clears out2 fault latches. x x <-0.3v no fault disables the output overvoltage and undervoltage fault circuitry. 1 1 v dd run (pwm) low noise low-noise operation with no automatic pwm/pfm switchover. fixed-frequency pwm action is forced regardless of load. inductor current reverses at light load levels. i dd draw <1.5ma (typ) plus gate-drive current. table 3. operating mode truth table 1 1 agnd run (pfm/pwm) normal operation with automatic pwm/pfm switchover for pulse-skipping at light loads. i dd <1.5ma (typ) plus gate drive current.
max1715 ultra-high efficiency, dual step-down controller for notebook computers 14 ______________________________________________________________________________________ nominal frequency setting (200khz, 300khz, 420khz, or 540khz), while the on-times for side 2 are set 15% lower than nominal. this is done to prevent audio-fre- quency ?eating?between the two sides, which switch asynchronously for each side: on-time = k (v out + 0.075v) / v in where k is set by the ton pin-strap connection and 0.075v is an approximation to accommodate for the expected drop across the low-side mosfet switch. one-shot timing error increases for the shorter on-time settings due to fixed propagation delays; it is approxi- mately ?2.5% at 540khz and 420khz nominal settings and ?0% at the two slower settings. this translates to reduced switching-frequency accuracy at higher fre- quencies (table 5). switching frequency increases as a function of load current due to the increasing drop across the low-side mosfet, which causes a faster inductor-current discharge ramp. the on-times guaran- teed in the electrical characteristics are influenced by switching delays in the external high-side power mos- fet. two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and pc board resistance) and the dead-time effect. these effects are the largest con- tributors to the change of frequency with changing load current. the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times. it occurs only in pwm mode ( skip = high) when the inductor current reverses at light or neg- ative load currents. with reversed inductor current, the inductor? emf causes lx to go high earlier than nor- mal, extending the on-time by a period equal to the low-to-high dead time. for loads above the critical conduction point, the actual switching frequency is: where v drop 1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; vdrop2 is the sum of the resistances in the charging path; and t on is the on-time calculated by the max1715. automatic pulse-skipping switchover in skip mode ( skip low), an inherent automatic switchover to pfm takes place at light loads. this switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between con- tinuous and discontinuous inductor-current operation (also known as the ?ritical conduction?point). for a battery range of 7v to 24v, this threshold is relatively constant, with only a minor dependence on battery volt- age. where k is the on-time scale factor (table 5). the load- current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple cur- rent, which is a function of the inductor value (figure 4). for example, in the standard application circuit with v out1 = 2.5v, v in = 15v, and k = 2.96? (see table 5), switchover to pulse-skipping operation occurs at i load = 0.7a or about 1/6 full load. the crossover point occurs at an even lower value if a swinging (soft-satura- tion) inductor is used. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping i kv 2l v-v v load(skip) out_ in out in ? ? ? ? ? ? ? f vv tv v out drop on in drop = + + () 1 2 good operating point for compound buck designs or desktop circuits. +5v input 540 420 3-cell li+ notebook useful in 3-cell systems for lighter loads than the cpu core or where size is key. considered mainstream by current standards. 4-cell li+ notebook 300 200 4-cell li+ notebook use for absolute best efficiency. comments typical application nominal frequency (khz) table 4. frequency selection guidelines table 5. approximate k-factor errors ton setting min v in at v out = 2v (v) side 1 k factor (s) v cc 2.6 4.24 open 2.9 2.96 ref 3.2 2.08 gnd 3.6 1.63 approx k-factor error (%) ?0 ?0 ?2.5 ?2.5 side 2 k factor (s) 5.81 4.03 2.81 2.18
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 15 operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input voltage levels). dc output accuracy specifications refer to the trip level of the error. when the inductor is in continuous conduction, the output voltage will have a dc regulation higher than the trip level by 50% of the ripple. in discontinuous con- duction ( skip = agnd, light-loaded), the output voltage will have a dc regulation higher than the trip level by approximately 1.5% due to slope compensation. forced-pwm mode ( s s k k i i p p = high) the low-noise, forced-pwm mode ( skip = high) dis- ables the zero-crossing comparator, which controls the low-side switch on-time. this causes the low-side gate- drive waveform to become the complement of the high- side gate-drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop strives to maintain a duty ratio of v out /v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no- load battery current can be 10ma to 40ma, depending on the external mosfets. forced-pwm mode is most useful for reducing audio- frequency noise, improving load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applications that use a flyback trans- former or coupled inductor. current-limit circuit (ilim) the current-limit circuit employs a unique ?alley?current- sensing algorithm that uses the on-state resistance of the low-side mosfet as a current-sensing element. if the current-sense signal is above the current-limit threshold, the pwm is not allowed to initiate a new cycle (figure 5). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple cur- rent. therefore, the exact current-limit characteristic and maximum load capability are a function of the mosfet on-resistance, inductor value, and battery voltage. the reward for this uncertainty is robust, lossless overcurrent sensing. when combined with the undervoltage protec- tion circuit, this current-limit method is effective in almost every circumstance. there is also a negative current limit that prevents exces- sive reverse inductor currents when v out is sinking cur- rent. the negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ilim is adjusted. the current-limit threshold is adjusted with internal 5? current source and an external resistor at ilim. the current-limit threshold adjustment range is from 50mv to 200mv, corresponding to resistor values of 100k ? to 400k ? . in the adjustable mode, the current-limit thresh- old voltage is precisely 1/10 the voltage seen at ilim. the threshold defaults to 100mv when ilim is connect- ed to v cc . the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. the adjustable current limit accommodates mosfets with a wide range of on-resistance characteristics (see design procedure ). carefully observe the pc board layout guidelines to ensure that noise and dc errors don? corrupt the cur- rent-sense signals seen by lx and pgnd. mount or figure 4. pulse-skipping/discontinuous crossover point inductor current i load = i peak /2 on-time 0 time -i peak l v batt -v out ? i ? t = figure 5. valley current-limit threshold point inductor current i limit i load 0 time -i peak
max1715 ultra-high efficiency, dual step-down controller for notebook computers 16 ______________________________________________________________________________________ place the ic close to the low-side mosfet with short, direct traces, making a kelvin sense connection to the source and drain terminals. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving mod- erate-size, high-side and larger, low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v batt - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high- side fet from turning on until dl is fully off. there must be a low-resistance, low-inductance path from the dl driver to the mosfet gate for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the max1715 will interpret the mosfet gate as ?ff while there is actually still charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the mosfet is 1 inch from the max1715). the dead time at the other edge (dh turning off) is determined by a fixed 35ns (typ) internal delay. the internal pull-down transistor that drives dl low is robust, with a 0.5 ? typical on-resistance. this helps prevent dl from being pulled up during the fast rise- time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous- rectifier mosfet. however, for high-current applica- tions, you might still encounter some combinations of high- and low-side fets that will cause excessive gate- drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with bst, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 6). por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and soft-start counter and preparing the pwm for operation. v cc undervoltage lockout (uvlo) circuitry inhibits switching and forces the dl gate driver high (to enforce output overvoltage protection) until v cc rises above 4.2v, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. the ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%; 100% current is available after 1.7ms ?0%. a continuously adjustable analog soft-start function can be realized by adding a capacitor in parallel with the ilim external resistor. this soft-start method requires a minimum interval between power-down and power-up to discharge the capacitor. power-good output (pgood) the output voltage is continuously monitored for under- voltage by the pgood comparator. in shutdown, soft- start, and standby modes, pgood is actively held low. after digital soft-start has terminated, pgood is released if both the outputs are within 5.5% of the error comparator threshold. the pgood output is a true open-drain type with no parasitic esd diodes. note that the pgood undervoltage detector is completely independent of the output uvp fault detector. output overvoltage protection (ovp) the overvoltage protection circuit is designed to pro- tect against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the output voltage is continuously monitored for overvoltage. if the output is more than 10.5% above the trip level of the error amplifier, ovp is triggered and the circuit shuts down. the dl low-side gate-driver output is then latched high until shdn is toggled or v cc power is cycled below 1v. this action turns on the synchronous- rectifier mosfet with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output to ground. if the condition that caused the over- voltage (such as a shorted high-side mosfet) per- sists, the battery fuse will blow. dl is also kept high continuously when v cc uvlo is active, as well as in shutdown mode (table 3). note that dl latching high causes the output voltage to go slightly negative, due to energy stored in the output lc at the instant ovp activates. if the load can? toler- ate being forced to a negative voltage, it may be desir- able to place a power schottky diode across the output to act as a reverse-polarity clamp (figure 1). bst +5v v in 5 ? dh lx max1715 figure 6. reducing the switching-node rise time
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 17 overvoltage protection can be defeated through the skip test mode (table 3). output undervoltage protection (uvp) the output undervoltage protection function is similar to foldback current limiting, but employs a timer rather than a variable current limit. if the max1715 output volt- age is under 70% of the nominal value 20ms after com- ing out of shutdown, the pwm is latched off and won? restart until v cc power is cycled or shdn is toggled. no-fault test mode the over/undervoltage protection features can compli- cate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a test mode is provided to totally disable the ovp, uvp, and thermal shutdown features, and clear the fault latch if it has been set. the pwm operates as if skip were grounded (pfm/pwm mode). the no-fault test mode is entered by sinking 1.5ma from skip through an external negative voltage source in series with a resistor (figure 7). skip is clamped to agnd with a silicon diode, so choose the resistor value equal to (v force - 0.65v) / 1.5ma. __________________design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: 1) input voltage range. the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to con- nectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. 2) maximum load current. there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com- ponents. modern notebook cpus generally exhibit i load = i load(max) 80%. 3) switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due to rapid improvements in mosfet technology that are mak- ing higher frequencies more practical (table 4). 4) inductor operating point. this choice provides trade-offs between size vs. efficiency. low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the circuit to operate at the edge of criti- cal conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the max1715? pulse-skipping algorithm initiates skip mode at the critical conduction point. so, the inductor operating point also determines the load- current value at which pfm/pwm switchover occurs. the optimum point is usually found between 20% and 50% ripple current. approximately -0.65v 1.5ma v force skip agnd max1715 figure 7. disabling over/undervoltage protection (test mode)
max1715 ultra-high efficiency, dual step-down controller for notebook computers 18 ______________________________________________________________________________________ the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maxi- mum duty factor, which can be calculated from the on- time and minimum off-time: where where minimum off-time = 400ns typ (see table 5). inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as fol- lows: example: i load(max) = 8a, v in = 7v, v out = 1.6v, f = 300khz, 35% ripple current or lir = 0.35: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice; although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): i peak = i load(max) + [(lir / 2) i load(max) ] determining the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: i limit(low) > i load(max) - (lir / 2) i load(max) where i limit(low) = minimum current-limit threshold voltage divided by the r ds(on) of q2. for the max1715, the minimum current-limit threshold (100mv default setting) is 90mv. use the worst-case maximum value for r ds(on) from the mosfet q2 data sheet, and add some margin for the rise in r ds(on) with tempera- ture. a good general rule is to allow 0.5% additional resistance for each ? of temperature rise. examining the 8a circuit example with a maximum r ds(on) = 12m ? at high temperature reveals the fol- lowing: i limit(low) = 90mv / 12m ? = 7.5a 7.5a is greater than the valley current of 6.6a, so the circuit can easily deliver the full-rated 8a using the default 100mv nominal ilim threshold. output capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition with- out tripping the overvoltage protection circuit. in cpu v core converters and other applications where the output is subject to violent load transients, the out- put capacitor? size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor? size depends on how much esr is needed to maintain an acceptable level of output voltage ripple: the actual microfarad capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and volt- age rating rather than by capacitance value (this is true of tantalums, os-cons, and other electrolytics). when using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent vsag and vsoar from causing problems during load tran- sients. also, the capacitance must be great enough to prevent the inductor? stored energy from launching the output above the overvoltage protection threshold. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the vsag equa- tion in the design procedure ). r vp p lir i esr load max ? - () r v i esr dip load max () l 1.6v (7 - 1 6) 7 300khz 0.33 8a 1.6 h == ? ??? l = v(v- v) v f lir i out in out in load(max) ?? ? duty k (v + 0.075v) v k (v + 0.075v) v + min off - time out in out out = v il c duty v v sag load max f in min out = ? ?? () () () () ? - 2 2
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 19 the amount of overshoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. output capacitor stability considerations stability is determined by the value of the esr zero rel- ative to the switching frequency. the point of instability is given by the following equation: where: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero fre- quencies of 15khz. in the design example used for inductor selection, the esr needed to support 50mvp-p ripple is 50mv/3.5a = 14.2m ? . three 470?/4v kemet t510 low-esr tantalum capacitors in parallel provide 15m ? max esr. their typical combined esr results in a zero at 14.1khz, well within the bounds of stability. don? put high-value ceramic capacitors directly across the fast feedback inputs (fb_ to agnd) without taking precautions to ensure stability. large ceramic capaci- tors can have a high-esr zero frequency and cause erratic, unstable operation. however, it? easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and fb_ pin (see the all-ceramic-capacitor application section). unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feed- back loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there isn? enough volt- age ramp in the output voltage signal. this ?ools?the error comparator into triggering a new cycle immedi- ately after the 400ns minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can trip the overvolt- age protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the max1715 ev kit manual) and carefully observe the out- put voltage ripple envelope for overshoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. don? allow more than one cycle of ringing after the initial step-response under- or overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (irms) imposed by the switching currents. nontantalum chemistries (ceramic, aluminum, or os- con) are preferred due to their resistance to power up surge currents. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>5a) when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. for maximum efficiency, choose a high-side mosfet (q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15v). check to ensure that the conduction losses at the minimum input voltage don? exceed the package thermal limits or violate the overall thermal budget. check to ensure that conduction losses plus switching losses at the maximum input voltage don? exceed the package rat- ings or violate the overall thermal budget. choose a low-side mosfet (q2) that has the lowest possible r ds(on) , comes in a moderate to small pack- age (i.e., so-8), and is reasonably priced. ensure that the max1715 dl gate driver can drive q2; in other words, check that the gate isn? pulled up by the high- side switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. switching losses aren? an issue for the low-side mos- fet since it? a zero-voltage switched device when used in the buck topology. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet, the worst-case- i i vv-v v rms load out in out in = () ? ? ? ? ? ? ? ? f rc esr esr f = ?? ? 1 2 f f esr = ? v li 2 2cv peak out
max1715 ultra-high efficiency, dual step-down controller for notebook computers 20 ______________________________________________________________________________________ power dissipation (pd) due to resistance occurs at minimum battery voltage: generally, a small high-side mosfet is desired in order to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation limits often limits how small the mos- fet can be. again, the optimum occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. high-side switching losses don? usually become an issue until the input is greater than approxi- mately 15v. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the cv 2 f switching loss equation. if the high-side mosfet you?e chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , reconsider your choice of mosfet. calculating the power dissipation in q1 due to switch- ing losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn- off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching loss calculation provides only a very rough estimate and is no substitute for bread- board evaluation, preferably including a verification using a thermocouple mounted on q1: where c rss is the reverse transfer capacitance of q1 and i gate is the peak gate-drive source/sink current (1a typ). for the low-side mosfet, q2, the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, you must ?verdesign?the circuit to tolerate: i load = i limit(high) + (lir / 2) ?i load(max) where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. this means that the mosfets must be very well heatsinked. if short-cir- cuit protection without overload protection is enough, a normal i load value can be used for calculating com- ponent stresses. choose a schottky diode (d1) having a forward voltage low enough to prevent the q2 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional and can be removed if efficiency isn? critical. _________________application issues dropout performance the output voltage adjust range for continuous-con- duction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. for best dropout performance, use the slowest (200khz) on- time setting. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the ton k-factor. this error is greater at higher fre- quencies (table 5). also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the vsag equation in the design procedure ). dropout design example: v in = 3v min, v out = 2v, f = 300khz. the required duty is (v out + v sw ) / (v in - v sw ) = (2v + 0.1v) / (3.0v - 0.1v) = 72.4%. the worst- case on-time is (v out + 0.075) / v in ?k = 2.075v / 3v 3.35?-v ?90% = 2.08?. the ic duty-factor limitation is: which meets the required duty. remember to include inductor resistance and mosfet on-state voltage drops (v sw ) when doing worst-case dropout duty-factor calculations. all-ceramic-capacitor application ceramic capacitors have advantages and disadvan- tages. they have ultra-low esr and are noncom- bustible, relatively small, and nonpolarized. they are also expensive and brittle, and their ultra-low esr char- acteristic can result in excessively high esr zero fre- quencies (affecting stability). in addition, their relatively low capacitance value can cause output overshoot duty t tt 2.08 s 2.08 s 500ns 80.6% on(min) on(min) off(max) = + = + = pd(q2) 1 - v v i r out in max load 2 ds on = ? ? ? ? ? ? ? ? () () ? pd(q1 switching) cv fi i rss in(max) 2 load gate = ??? pd(q1 resistance) v v i r out in min load 2 ds on = ? ? ? ? ? ? ? ? () () ?
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 21 when going abruptly from full-load to no-load condi- tions, unless there are some bulk tantalum or electrolyt- ic capacitors in parallel to absorb the stored energy in the inductor. in some cases, there may be no room for electrolytics, creating a need for a dc-dc design that uses nothing but ceramics. the all-ceramic-capacitor application of figure 8 replaces the standard tantalum output capacitors with ceramics. this design relies on having a minimum of 5m ? parasitic pc board trace resistance in series with the capacitor to reduce the esr zero frequency. this small amount of resistance is easily obtained by locat- ing the max1714a circuit 2 or 3 inches away from the cpu, and placing all the ceramic capacitors close to the cpu. resistance values higher than 5m ? just improve the stability (which can be observed by exam- ining the load-transient response characteristic as shown in the typical operating characteristics ). avoid adding excess pc board trace resistance, as there? an efficiency penalty; 5m ? is sufficient for a 7a circuit: output overshoot ( ? v) determines the minimum output capacitance requirement. in this example, the switch- ing frequency has been increased to 600khz and the inductor value has been reduced to 0.5? (compared to 300khz and 2? for the standard 8a circuit) to mini- mize the energy transferred from inductor to capacitor during load-step recovery. the overshoot must be cal- culated to avoid tripping the ovp latch. the efficiency penalty for operating at 540khz is about 2% to 3%, depending on the input voltage. an optional 1 ? resistor is placed in series with out. this resistor attenuates high-frequency noise in some bands, which causes double pulsing. fixed output voltages the max1715? dual mode operation allows the selection of common voltages without requiring external components (figure 9). connect fb to agnd for a fixed +2.5v output or to v cc for a +3.3v output, or con- nect fb directly to out for a fixed +1.0v output. setting v out with a resistor-divider the output voltage can be adjusted with a resistor- divider if desired (figure 8). the equation for adjusting the output voltage is: where v fb is 1.0v and r2 is about 10k ? . two-stage (5v-powered) notebook cpu buck regulator the most efficient and overall cost-effective solution for stepping down a high-voltage battery to a very low out- put voltage is to use a single-stage buck regulator that? powered directly from the battery. however, there may be situations where the battery bus can? be routed near the cpu, or where space constraints dictate the smallest possible local dc-dc converter. in such cases, the 5v-powered circuit of figure 10 may be appropriate. the reduced input voltage allows a higher v v 1 r1 r2 out fb =+ ? ? ? ? ? ? r 1 2fc esr out max1715 to error amp1 to error amp2 out2 fb2 0.2v 0.2v 2v fb1 fixed 2.5v fixed 1.8v fixed 3.3v out1 figure 9. feedback mux dl agnd out pgnd dh 1/2 fb v batt v out r1 r2 max1715 figure 8. setting v out with a resistor-divider dual mode is a trademark of maxim integrated products.
max1715 ultra-high efficiency, dual step-down controller for notebook computers 22 ______________________________________________________________________________________ switching frequency and a much smaller inductor value. pc board layout guidelines careful pc board layout is critical to achieving low switching losses and clean, stable operation. this is especially true for dual converters, where one channel can affect the other. the switching power stages require particular attention (figure 11). refer to the max1715 ev kit data sheet for a specific layout example. if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for good pc board layout: isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. use a separate pgnd plane under the out1 and out2 sides (called pgnd1 and pgnd2). avoid the introduction of ac currents into the pgnd1 and pgnd2 ground planes. run the power plane ground currents on the top side only, if possible. use a star ground connection on the power plane to minimize the crosstalk between out1 and out2. keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. tie agnd and pgnd together close to the ic. do not connect them together anywhere else. carefully follow the grounding instructions under step 4 of the layout procedure . keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. lx_ and pgnd connections to the synchronous rec- tifiers for current limiting must be made using kelvin sense connections to guarantee the current-limit accuracy. with so-8 mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while tying in pgnd and lx_ inside (underneath) the so-8 package. when trade-offs in trace lengths must be made, it? preferable to allow the inductor charging path to be ilim v cc v in 4.5v to 5.5v l1 0.5 h v out 2.5v at 7a on2 1 f 0.1 f 0.22 f c2 3 x 470 f kemet t510 irf7805 irf7805 1 f20 ? c1 4 x 10 f/25v on/off dl2 lx2 bst2 dh2 pgnd out2 fb2 agnd v dd v cc v+ max1715 ref ton skip 100k pgood figure 10. 5v-powered, 8a cpu buck regulator
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 23 made longer than the discharge path. for example, it? better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ensure that the out connection to c out is short and direct. however, in some cases it may be desirable to deliberately introduce some trace length between the out inductor node and the output filter capacitor (see the all-ceramic-capacitor application section). route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, ilim, fb). use pgnd1 and pgnd2 as emi shields to keep radiated switching noise away from the ic, feedback dividers, and analog bypass capacitors. make all pin-strap control input connections ( skip , ilim, etc.) to agnd or v cc rather than pgnd_or v dd . layout procedure 1) place the power components first, with ground termi- nals adjacent (q2 source, c in -, c o ut -, d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the synchronous rectifiers mosfets, preferably on the back side in order to keep lx_, pgnd_, and the dl_ gate-drive line short and wide. the dl_ gate trace must be short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the mosfet is 1 inch from the controller ic). 3) group the gate-drive components (bst_ diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as follows: near the ic, create a small analog ground plane. connect this plane to agnd and use this plane for the ground connection for the ref and v cc bypass capacitors, fb dividers, and i lim resis- tors (if any). create another small ground island for pgnd, and use it for the v dd bypass capacitor, placed very close to the ic. connect the agnd and the pgnd pins together under the ic (this is the only connection between agnd and pgnd). 5) on the board? top side (power planes), make a star ground to minimize crosstalk between the two sides. the top-side star ground is a star connection of the input capacitors, side 1 low-side mosfet, and side 2 low-side mosfet. keep the resistance low between the star ground and the source of the low- side mosfets for accurate current limit. connect the top-side star ground (used for mosfet, input, and output capacitors) to the small pgnd island with a short, wide connection (preferably just a via). if multiple layers are available (highly recommend- ed), create pgnd1 and pgnd2 islands on the layer just below the top-side layer (refer to the max1715 ev kit for an example) to act as an emi shield. connect each of these individually to the star ground via, which connects the top side to the pgnd plane. add one more solid ground plane under the ic to act as an additional shield, and also connect that to the star ground via. 6) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. agnd pgnd via to out1 ground out2 out1 via to out2 via to pgnd via to lx1 v in via to lx2 use agnd plane to: - bypass v cc and ref - terminate external fb divider (if used) - terminate r ilim (if used) - pin-strap control inputs use pgnd plane to: - bypass v dd - connect pgnd to the topside star ground via to ground note: example shown is for dual n-channel mosfet. connect pgnd to agnd beneath the max1715 at one point only as shown. c4 c3 c1 n1 d1 d2 n2 c2 l1 l2 figure 11. pc board layout example
max1715 ultra-high efficiency, dual step-down controller for notebook computers 24 ______________________________________________________________________________________ pin configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n.c. lx1 dh1 bst1 dl1 n.c. n.c. pgnd v cc v dd dl2 bst2 dh2 lx2 out2 fb2 ilim2 on2 on1 ref agnd pgood skip ton v+ ilim1 fb1 out1 qsop top view max1715
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 25 package information qsop.eps
max1715 ultra-high efficiency, dual step-down controller for notebook computers 26 ______________________________________________________________________________________ notes
max1715 ultra-high efficiency, dual step-down controller for notebook computers ______________________________________________________________________________________ 27 notes
max1715 ultra-high efficiency, dual step-down controller for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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